High-speed ADCs are important in a wide variety of commercial applications including data communications and image signal processing. In such applications, the reduction of power consumption associated with high-speed sampling and quantization is one key design issue in enhancing portability and battery operation.
In general, pipelined ADCs are very efficient architectures for meeting the low power dissipation and high input bandwidth requirements of these applications. In a pipelined ADC, op-amps are used in the first stage to sample the high frequency input and also in the subsequent stages to sample the residue from the previous stage. This feature allows each stage of the pipeline to begin processing a new sample as soon as its residue is sampled by the following stage, and also allows all stages to operate concurrently, giving a throughput of one output sample per clock cycle. Thus, pipelined ADCs can operate at high sampling rates with high dynamic range.
To further reduce power consumption of a pipelined ADC, an op-amp can be shared between two successive pipeline stages to obtain a power-efficient architecture. Due to the switched-capacitor architecture of general pipelined ADC, every op-amp is occupied for only half clock cycle, the multiplying digital-to-analog conversion (MDAC) phase, and is idle in another half clock cycle. Therefore, the same op-amp can be shared between two consecutive pipeline stages by adding more switches.
However, op-amp sharing has an inherent drawback. Since the input node of the op-amp is never reset, the MDAC output depends on the previous residue, thus degrading the linearity of the overall converter. This is often referred to as memory effect. Op-amp sharing introduces the memory effect as the nonzero input voltage of the op-amp (resulting from its finite gain) is never reset. Thus, every input sample is affected by the finite-gain error component from the previous sample. The memory effect between the first two MSB conversion stages is particularly detrimental.
This memory effect can be suppressed by resetting the op-amp input before sampling the ADC input. The timing for the reset signal can be made between the two clock phases as shown in FIGS. 1A-1D. FIG. 1A depicts a timing diagram for the clock Ø1 for the first phase, the clock Ø2 for the second phase, and the reset signal ØDS. FIG. 1B depicts the first phase when Ø1 is high. FIG. 1C depicts the reset stage. FIG. 1D depicts the second phase when Ø2 is high. The drawback associated with the architecture of FIGS. 1A-1D is the additional clock phase, the reduction of conversion time, and the fast settling requirement of op-amp.
In order to solve this problem, some people propose a feedback signal polarity inverting technique between two sharing phases, as shown in FIGS. 2A-2B. FIG. 2A depicts the first phase, and FIG. 2B depicts the second phase. With the feedback signal polarity inverting technique, the error voltage of the given op-amp sharing stage can be reduced to one third of the conventional error voltage. FIGS. 2A-2B show how to implement this technique.
The memory effects of op-amp sharing can also be mitigated with a low input-capacitance op-amp. The low input-capacitance op-amp is shown in FIG. 3. The op-amp is based on pre-amplification and has the desirable property of having a low input-capacitance. Lower input capacitance helps to increase the feedback factor and reduce memory effects. However, a non-dominant pole associated with the preamplifier output node will reduce the phase margin.
What is needed is a method and system of op-amp sharing without the drawbacks found in the prior art, such as the memory effect.